As is known in the art, many data systems include Double Data Rate (DDR) SDRAM memories. In many data systems several DDR SDRAM chips are used. Reading of data from a DDR SDRAM memory system is accomplished with each SDRAM chip producing in response to a read command its own read strobe pulse. The read strobe pulse from each chip is used to strobe the data, typically a nibble, read from that chip into a storage device (i.e., sampler) associated with that chip. The read strobe is produced at the leading edge of a valid data window, or eye, of the data, i.e., nibble. While ideally, in response to the read data command, all of the chips in the memory system should provide the data read therefrom to a data bus at the same time and produce all of the read strobe pulses at the same time, because of chip mismatches, board layout and internal timing skews, the data provided on the data bus from each of the chips may have time delays one from the other and the read strobe pulses may also have time delays one from the other.
It is also known in the art that it is desirable to strobe the data into the sampler at the center of the valid data window the strobe which, as noted above is delayed one half of the window period. This one-half period delay is applied to all the read strobe pulses. Therefore, because of the variation in the time each nibble is provided to its sampler and the time variations of the read strobe pulses, valid data may not be sampled into one or more of the samplers.